1. Field of the Invention
The invention relates to an actuating circuit for a three-level inverter.
2. Description of the Related Art
The invention is directed to an actuating circuit having a plurality of level shifters for transmitting actuation signals from an actuating logic circuit with a first reference potential to driver stages with at least partially different further reference potentials. In principle, such actuation circuits are required in power electronics systems to actuate semiconductor switches which are arranged as individual switches or in a bridge circuit. Such bridge circuits are known as single-phase, two-phase or three-phase bridge circuits, wherein the single-phase so-called half-bridge circuit is a basic component of a multiplicity of power electronics circuits. In a two-level half-bridge circuit, two semiconductor switches—a first, lower, so-called BOT switch and a second, upper, so-called TOP switch—are arranged in a manner connected in a series circuit. Such a half-bridge generally has a connection to a DC voltage intermediate circuit. The output, designed as AC voltage connection of the half-bridge is usually connected to a load according to the state of the art.
By alternately switching TOP and BOT switches, the output voltage of the half-bridge circuit varies between the fixed voltage values of the positive and negative voltage connections to the intermediate circuit. Since two static voltage states thus exist, this half-bridge circuit is referred to as two-level half-bridge circuit or two-level inverter.
In addition to the two-level half-bridge circuit, more complex bridge circuits are also known, to which three or more static voltage states can be switched. These are referred to as multi-level inverters. The advantage of multi-level inverters is that the profile of the output voltage can be approximated more closely to the desired sinusoidal profile. In this way, the total harmonic distortion (THD) of the output current can be reduced, as a result of which smaller and more inexpensive grid filters can be used. By the same token, the same THD values can be achieved at a lower switching frequency by use of multi-level inverters over two-level inverters, as a result of which lower switching losses occur. However, the increased expenditure for closed-loop control and the higher number of necessary components and actuating circuits are disadvantageous in the case of multi-level inverters.
The simplest configuration of a multi-level inverter is the three-level inverter with three switchable voltage states. In principle, two topologies are known for three-level inverters, the common feature of which is that, according to the state of the art, they are usually supplied by two series-connected high-voltage intermediate circuits via a positive and a negative connection. The center point of the series circuit is referred to as the neutral node and is usually at ground potential according to the state of the art. The neutral node is also used as the third voltage state.
According to the state of the art, actuating circuits for three-level inverters are usually embodied with galvanic isolation between a primary side and a plurality of secondary sides. The actuating circuit in this case consists of a plurality of partial circuits or functional blocks. The actuation signals of a superordinate control logic circuit, for example a microcontroller, are processed in a first primary-side circuit part of the actuating logic circuit. The reference potential of the primary-side circuit part is in this case at the grounded neutral node. The transmission of the actuation signals to the secondary-side circuit parts takes place in an electrically isolated manner via impulse transmitters which operate by transformer action or optically via optocouplers or optical waveguides. The driver stages as part of the secondary-side circuit part control the semiconductor switches, for example IGBTs, according to the transmitted signals.
In principle, all of the primary-side and the respective secondary-side functions can be brought together in monolithically integrated circuits. However, according to the state of the art, the required galvanically isolating potential isolation members are not integrable, with the result that the functional blocks of the primary-side circuit part and the secondary-side circuit part are usually constructed discretely together with the potential isolation member on a PCB (printed circuit board).
For two-level inverters, actuating circuits with potential isolation in integrated circuit technology, for example in a high-voltage integrated circuit (HVIC), are known in principle. HVICs are increasingly used since they offer certain advantages, such as low volume, low price and long service life. In this case, HVICs firstly offer the opportunity to realize the potential isolation between the primary-side actuating circuit and the secondary-side driver circuit, and secondly to integrate a level shifter with a high-voltage component having a breakdown voltage of the HVIC corresponding to the potential difference, which can be used to transmit signals between the primary-side and the secondary-side circuit part.
A level shifter of this type can be embodied as part of the actuating circuit and integrated in the HVIC. It is used to transmit a signal from a primary-side circuit part with a defined reference potential to a secondary-side circuit part with a temporarily higher or lower reference potential.
Furthermore, in principle, two isolation technologies are known for forming HVICs: firstly, the SOI (silicon on insulator) technologies, and secondly p-n-isolated technologies (junction isolation). SOI technology offers a dielectric potential isolation of components or groups of components, but is only available at present up to 800 V potential difference owing to the limited dielectric strength. In the case of p-n-isolated technologies, the potential difference of a reverse-biased p-n junction is incorporated. At present, this technology is available up to 1200 V potential difference.
A simple configuration of a level shifter consists of a high-voltage transistor (HV transistor) with the blocking ability which corresponds to the potential difference to be bridged and a resistor connected in series. If a signal is passed to the gate of the HV transistor on the primary-side circuit part, the HV transistor switches on. The transverse current thus generated through the level shifter causes a voltage drop across the resistor, which voltage drop can be detected as a signal by an evaluation circuit on the secondary-side circuit part. Such level shifters with HV transistors comprise, in principle, a transverse current path necessary for signal transmission, with the result that a potential isolation but no galvanic isolation is present.
German published patent application DE 101 52 930 A1 discloses an extended level shifter topology in which the actuation signal is transmitted in steps via intermediate potentials by means of a plurality of identical cascade-connected level shifters. Hence, transistors which only have a fraction of the required blocking ability of the overall level shifter can be used. Thus, the blocking ability of the level shifter can be significantly increased.
German published patent application DE 10 2006 037 336 A1 discloses a level shifter embodied as a series circuit composed of HV transistors of the n-channel type. This topology has the advantages that, in contrast to that according to DE 101 52 930 A1, firstly the power consumption and secondly the switching expenditure are reduced. This results, in particular, in a lower requirement on space.
It is a common feature of all of the mentioned configurations of HVICs that, in the case of complementary construction of the level shifter, a signal transmission from a circuit part with a high reference potential to a circuit part with a low reference potential is possible in principle. This property can thus be used for a reverse signal transmission from the secondary-side circuit part to the primary-side circuit part and thus for the actuating logic circuit there. However, an HV transistor of the p-channel type is required for this purpose.
Parasitic inductances of a system composed of a power semiconductor module and an actuating circuit may result in severe chopping of the respective reference potential of the secondary-side circuit parts, usually in the positive direction but also negative direction, below the actuation-side reference potential during rapid switching of the power switches. This occurs particularly severely in medium- and high-power systems, in which large currents, in particular currents greater than 50 A, are switched. However, most level shifters which are currently available are not configured for signal transmission of this type in the negative direction. Also, the known p-n isolation technologies have the disadvantage that, in the case of a corresponding chopping of the reference potential in the negative direction, the blocking ability between the primary-side and the secondary-side circuit part is lost and the flowing leakage current can lead to parasitic thyristor structures being triggered, so-called latch-up. This leads to a loss of function and, possibly, to destruction of the circuits in question.
Circuits utilizing SOI technologies do not suffer from these drawbacks, owing to the dielectric isolation and the bidirectional blocking ability connected therewith of the isolation regions, with the result that transmission circuits which ensure a reliable signal transmission and isolation are realizable in terms of circuitry, even in the event of temporary or permanent negative secondary-side reference potential. German published patent application DE 10 2006 050 913 A1 discloses such a level shifter for a BOT secondary-side embodied in SOI technology with in each case an UP and DOWN level shifter branch, while German published patent application DE 10 2007 006 319 A1 discloses such a level shifter for a TOP secondary-side likewise embodied in SOI technology as UP and DOWN level shifter branch.